Add FPGA memory access via vector unit test

Change-Id: Ifa5a22431cf9c874992807eb96084c0dabf4e00d

libnux/dls_vx.h

@@ -31,6 +31,7 @@ static uint32_t const dls_config_even_base    = 0x00010000;
 static uint32_t const dls_config_odd_base     = 0x00020000;
 static uint32_t const dls_raw_base            = 0x000f0000;
 static uint32_t const dls_randgen_base        = 0x000e0000;
+static uint32_t const dls_extmem_base         = 0x80000000;
 
 /* Byte to be written to synapse for correlation reset */
 static uint8_t const dls_correlation_reset = 0x3;

libnux/vector.h

@@ -130,4 +130,44 @@ inline vector_row_t get_row_via_omnibus(size_t const row, uint32_t const base)
 	return ret;
 }
 
+
+vector_type get_vector(uint32_t base, uint32_t index)
+{
+	uint32_t zero = 0;
+	vector_type values;
+	asm volatile(
+	    // clang-format off
+		"fxvinx %1, %[base], %[index]\n"
+		"fxvstax %1, %[sindex], %[zero]\n"
+		"sync\n"
+		: "+m"(const_cast<vector_type &>(values))
+		: [base] "b" (base),
+		  [index] "r" (index),
+		  [sindex] "r" (values.data()),
+		  [zero] "r" (zero)
+		: /* no clobber */
+	    // clang-format on
+	);
+	return values;
+}
+
+void set_vector(vector_type const& values, uint32_t base, uint32_t index)
+{
+	uint32_t zero = 0;
+	asm volatile(
+	    // clang-format off
+		"fxvlax %1, %[sindex], %[zero]\n"
+		"fxvoutx %1, %[base], %[index]\n"
+		"sync\n"
+		:
+		: [base] "b" (base),
+		  [index] "r" (index),
+		  [sindex] "r" (values.data()),
+		  [zero] "r" (zero),
+		  "m"(const_cast<vector_type &>(values))
+		: /* no clobber */
+	    // clang-format on
+	);
+}
+
 } // namespace libnux

test/test_fpga_memory_vector_access.cpp

+#include <array>
+#include <stddef.h>
+#include <stdint.h>
+#include "libnux/dls.h"
+#include "libnux/unittest.h"
+#include "libnux/vector.h"
+
+using namespace libnux;
+
+void start(void) {
+	libnux_test_init();
+
+	libnux_testcase_begin("external memory write read via vector unit");
+	vector_type values;
+	for (size_t entry = 0; entry < dls_vector_size; ++entry) {
+		values[entry] = entry;
+	}
+
+	uint32_t const index = 0;
+
+	set_vector(values, dls_extmem_base, index);
+
+	auto const read = get_vector(dls_extmem_base, index);
+
+	for (size_t column = 0; column < 128; ++column) {
+		libnux_test_equal(read[column], values[column]);
+	}
+	libnux_testcase_end();
+
+	libnux_test_summary();
+	libnux_test_shutdown();
+}

wscript

@@ -169,6 +169,11 @@ def build(bld):
                 'test/test_vector_sync.cpp',
                 'test/test_xorshift_vector.cpp',
             ]
+        else:
+            # These tests only work for HX
+            program_list += [
+                'test/test_fpga_memory_vector_access.cpp',
+            ]
 
         for program in program_list:
             bld.program(