* needed for run to terminate within gdb

Change-Id: Iacef0cf1cbcafe83b11068885bc1ac520a5a83da

* saves >200MB space on install

Change-Id: Ieca3ddf5ea245bddf6b8577ee3e67a145b97881e

Change-Id: Ieb32f507bc3a58a260f6648ca37224d30cc22c34

Change-Id: I9cc2524a50772b31160c76130bb65ef070e9887d

* use rant directly for only case (num-bits of JTAG data)
* use bitset for bit-aligned data in spike/MADC sample from chip

Depends-On: 10242
Change-Id: Ica7ea95caa84d228545ace9ff671f2a50940b39e

* each tuple of subword and phyword type and header alignment
  are compiled separately
* Reduces compile time from 5Min. to 1:30Min. with enough parallelism

Change-Id: Ia9083b26220a5ac2711d4fe0dcb07dea93037add

Change-Id: I8eea13138c555e0a4524ce7e44489d37a2b10996

Change-Id: Ic4cbc672f2a00cf0dae84e569e97b4582d564cf8

Change-Id: Ibd32b905a65a9b1083d1e1e5d3807f57da90c7b2

Eric Müller authored 5 years ago and Philipp Spilger committed 5 years ago

Depends-On: 9073
Change-Id: Ieb982f62b18875269bbaa628cf1fd54b536e16af

* moved from sctrltp

Change-Id: Idb4d908dd179aecefc1a18a317f936baee62b3a7

* spike payload is only 16-bit wide bitset

Depends-On: 8248,8366
Change-Id: Ica93c1a60f0b3bd02c8f50d7fcbd9d67de653b31

Change-Id: I72059b7a7dd11857b7af5a31bc6a46e157e8c258

* add custom macros to support compile-time disabling

Change-Id: I4a406613efb26375358fd5da672185f2fa0203bd

Depends-On: 8150
Change-Id: I82f3175bb852599ea37fdaa91e02ddd79869c291

* remove unused boost system dependency

Change-Id: I5d11faeae2d840b51eeeff129a13a2ba7fd31cdd

* fix operator== error of omnibus_to_fpga::Address

Change-Id: If830f8e3a49904383a20867f21bea7740dd98a10

* not needed due to flange python bindings

Change-Id: Ic2449924d81ac8291f933372493073baad8c539c

Change-Id: Id8ac4ebc736bbadb8a893a9ea894f3f8b9011c56

Change-Id: I50d9ad07db225321b233931e5f6d7ca8b6845f67

* add event packing to up to three for to FPGA spikes, from Chip spikes
  and MADC sample events
* add systime init and sys{time,delta} time response instructions

Depends-On: 6228
Change-Id: I97b3f2f4079bb7b8f469ee1d15b7134af294220f

Change-Id: I106020ea364734a2fb4c75dfedea51a115202d29

Change-Id: I43b269489cf8b2ad6c70e5585b21ec3aea724954

Yannik Stradmann authored 5 years ago and Yannik Stradmann committed 5 years ago

Change-Id: I0c205acb519a714de46a7548e5a8c973de957303

Change-Id: I9461176b6f59fca8a7f03f0a02289044956e6ac6

* rename simulation test folder hw -> sim
* move common test parameters ip, port to main file

Change-Id: I3390c1c644168d61d490fd9167053fee51049036

* typesafe UT message type unique to instruction
** parameterized on: header alignment, common div / subword width
   (limited to integer type width), instruction dictionary,
   instruction
* instruction: { size, payload_type }
* supported instructions:
** JTAG (clock-scaler, init, instr.-register, data, data-response)
** timing (wait_until, reset)
** system (reset, halt, halt-response)
* {ARQ, Sim, Loopback}-connection
** common base in common namespace
** (parameter-)specialization for vx in vx namespace
** 'add', 'commit' messages to send to backend
** 'receive', 'try_receive' messages to receive from backend
** blocking 'run_until_halt' blocking until 'halt' instruction
   decoded (not available for loopback connection)
* remove unused python bindings in hxcomm
  due to missing-namespace-errors in generated code

Change-Id: I419a72e4f3c9a8e1bb6a92114d5f1f7cd5658df9

Change-Id: If745edfff944db22729656aad266121639481b1e

Change-Id: Iad391077bc2e107f0b7e753b2f3ad5152f997e3d

* add derived shallow SimConnection in hxcomm
* HostARQ ut-message type chage 0x17a6 -> 0x0010

Change-Id: Ie2afdcb1a41eefa47788f68936e3c65daf3ef404

Eric Müller authored 6 years ago and Philipp Spilger committed 6 years ago

The C++ class is also accessible using C functions:
dpi_comm_{init,shutdown,tx,rx}

Change-Id: I5bfc43fc8f3239c330a799233874a18fd99e4d6b

Change-Id: Id091fa991e51edc5f65563fc5dd852da0ff9f1f1

Mitja Kleider authored 6 years ago and Philipp Spilger committed 6 years ago

Change-Id: I1932cbced2c2c86178cbed8d955c8c2acb174e4e

Mitja Kleider authored 6 years ago and Philipp Spilger committed 6 years ago

Change-Id: I902923bc1d3aa0b7b4cce615caca2f32f0a2ccc7

Yannik Stradmann authored 6 years ago and Yannik Stradmann committed 6 years ago

Make sure it
 * builds
 * without compiler warnings
 * without failing tests

More advanced features (we want clang-format checks!) might be added
later.

Change-Id: Ic8879b201f83212229e7fc108a1148891dc3beaf