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  • Yannik Stradmann's avatar
    Introduce vx::v3 namespaces · f2fef7b5
    Yannik Stradmann authored
    This change introduces namespaces for the upcoming
    HICANN-DLS-SR-HXv3 BrainScaleS-2 ASIC. All logic currently
    mirrors the implementation in HXv2.
    
    Once HXv3 is finalized, remaining common code should be moved
    to the (existing) common namespace.
    
    Change-Id: Ic3b6a1e9008ce56c140244a7e1e2e41dd9870086
    f2fef7b5
dlens_swtest_vx_v3.py 602 B
#!/usr/bin/env python
import unittest
from dlens_vx_v3 import halco, hal, sta, lola


class TestDlensVXV3(unittest.TestCase):
    def test_import(self):
        capmem_cell = hal.CapMemCell()
        self.assertIsNotNone(capmem_cell)

        builder = sta.PlaybackProgramBuilder()
        self.assertIsNotNone(builder)

        capmem_on_dls = halco.CapMemBlockOnDLS()
        self.assertIsNotNone(capmem_on_dls)

        enum = halco.common.Enum(2)
        self.assertIsNotNone(enum)

        row = lola.SynapseRow()
        self.assertIsNotNone(row)


if __name__ == "__main__":
    unittest.main()