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dlens_swtest_vx_v3.py
Yannik Stradmann authored
This change introduces namespaces for the upcoming HICANN-DLS-SR-HXv3 BrainScaleS-2 ASIC. All logic currently mirrors the implementation in HXv2. Once HXv3 is finalized, remaining common code should be moved to the (existing) common namespace. Change-Id: Ic3b6a1e9008ce56c140244a7e1e2e41dd9870086
dlens_swtest_vx_v3.py 602 B