cddc3bd16d Merge pull request #265 from upibhalla/master
5856ac1fa7 Fixes for travis.yml
219f474a2e Fix to HSolve to prevent segv during destruction. Update to rdesigneur to not create HSolve when turnOffElec flag is set
9ca16e8246 Merge branch 'master' of https://github.com/BhallaLab/moose-core
58e630b4dc Updates to the Voltage clamp modules. The key thing to note is to use the standalone VClamp object in preference to individually building the circuit with DiffAmp. RC and PID.
12cf83e17a Updates to Hsolve to be able to delete and recreate it. Still problematic for HHChannels. Also added Vclamp to the rdesigneurProtos.
3dc99b53e6 Changes made to object name which had number in starting
3ec52cd9e4 Small bugfix to rdesigneur
241c3d59cb Use sys.executable to execute test. It breaks on python3.
f527490ff0 Fixes to rdesigneur to use the new system for cross-compartment reactions
501ff45939 Major cleanup to get rid of legacy cross-compartment code
f4b4...