From 753dfd8646725e6bdbf67672875e5b5a98f54f8c Mon Sep 17 00:00:00 2001 From: Philipp Spilger <philipp.spilger@kip.uni-heidelberg.de> Date: Fri, 24 Jan 2020 11:09:02 +0100 Subject: [PATCH] Add CADC read test for fixture data in simulation Change-Id: I4b9cde62a9d46c025d41067a48790b1e3368352f --- libnux/dls_vx.h | 12 +++++++++ test/helpers/hwtest_common.py | 12 ++++++++- test/test_cadc.cpp | 50 +++++++++++++++++++++++++++++++++++ wscript | 1 + 4 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 test/test_cadc.cpp diff --git a/libnux/dls_vx.h b/libnux/dls_vx.h index 8cb36fe..b9a3dcd 100644 --- a/libnux/dls_vx.h +++ b/libnux/dls_vx.h @@ -59,3 +59,15 @@ static constexpr omnibus_address_t dls_spike_base = 0x1c000040ul; /* MADC and reference current generator configuration base address */ static constexpr omnibus_address_t madc_base_address = (1ul << 19 | 1ul << 18); + +/* Address of synram */ +static constexpr omnibus_address_t synram_top_base_address = 0x02800000 | (1 << 22); +static constexpr omnibus_address_t synram_bottom_base_address = 0x03800000 | (1 << 22); + +/* CADC causal base address for top PPU */ +static constexpr omnibus_address_t cadc_top_causal_base_address = + synram_top_base_address | dls_causal_base; + +/* CADC acausal base address for top PPU */ +static constexpr omnibus_address_t cadc_top_acausal_base_address = + synram_top_base_address | dls_acausal_base; diff --git a/test/helpers/hwtest_common.py b/test/helpers/hwtest_common.py index 021a9df..43f91df 100644 --- a/test/helpers/hwtest_common.py +++ b/test/helpers/hwtest_common.py @@ -93,7 +93,7 @@ def get_special_binaries(dls_version: str) -> Set[PpuHwTest]: stack_protection = os.environ.get("STACK_PROTECTION", "").lower() == "true" stack_redzone = os.environ.get("STACK_REDZONE", "").lower() == "true" - return { + test_list = { PpuHwTest( join(TEST_BINARY_PATH, f"test_unittest_{dls_version}.bin"), expected_exit_code=1), @@ -107,3 +107,13 @@ def get_special_binaries(dls_version: str) -> Set[PpuHwTest]: join(TEST_BINARY_PATH, f"test_stack_redzone_{dls_version}.bin"), expected_exit_code=12 if stack_redzone else 2) } + + if dls_version == 'vx': + simulation = os.environ.get("FLANGE_SIMULATION_RCF_PORT") + test_list.update({ + PpuHwTest( + join(TEST_BINARY_PATH, f"test_cadc_{dls_version}.bin"), + expected_exit_code=0 if simulation is not None else 1), + }) + + return test_list diff --git a/test/test_cadc.cpp b/test/test_cadc.cpp new file mode 100644 index 0000000..4784fd1 --- /dev/null +++ b/test/test_cadc.cpp @@ -0,0 +1,50 @@ +#include <array> +#include <stddef.h> +#include <stdint.h> +#include "libnux/dls.h" +#include "libnux/omnibus.h" +#include "libnux/unittest.h" +#include "libnux/vector.h" + + +using namespace libnux; + +// generated in hx_top/**/anncore.sv +vector_row_t get_expectation() +{ + vector_row_t ret; + + for (size_t col = 0; col < dls_num_columns; ++col) { + if (col % 2 == 0) { + ret.even_columns[col / 2] = 1 << 7 | ((col % 64) << 1); + } else { + ret.odd_columns[col / 2] = 1 << 7 | ((col % 64) << 1); + } + } + return ret; +} + +// program entry point +void start(void) +{ + libnux_test_init(); + + libnux_testcase_begin("cadc static pattern"); + auto const expectation = get_expectation(); + constexpr size_t row = 0; // arbitrary in [0,256) + std::array<bool, 2> is_causal = {false, true}; + for (auto const causal : is_causal) { + auto const cadc_vector = + get_row_via_vector(row, causal ? dls_causal_base : dls_acausal_base); + // static test pattern is same for both top and bottom tree, therefore only top + // is tested here + auto const cadc_omnibus = get_row_via_omnibus( + row, causal ? cadc_top_causal_base_address : cadc_top_acausal_base_address); + libnux_test_equal(cadc_vector, cadc_omnibus); + libnux_test_equal(cadc_vector, expectation); + } + libnux_testcase_end(); + + libnux_test_summary(); + libnux_test_shutdown(); +} diff --git a/wscript b/wscript index c5b28d2..8ea0e19 100644 --- a/wscript +++ b/wscript @@ -172,6 +172,7 @@ def build(bld): else: # These tests only work for HX program_list += [ + 'test/test_cadc.cpp', 'test/test_fpga_memory_vector_access.cpp', ] -- GitLab