diff --git a/include/halco/hicann-dls/vx/fpga.h b/include/halco/hicann-dls/vx/fpga.h
index 5e88ac20b11e6b7134106d800705d9aed388d323..92d4cb952884a0bcd41bb64a211112e8a556797b 100644
--- a/include/halco/hicann-dls/vx/fpga.h
+++ b/include/halco/hicann-dls/vx/fpga.h
@@ -146,6 +146,20 @@ struct GENPYBIND(inline_base("*")) InstructionTimeoutConfigOnFPGA
 	constexpr explicit InstructionTimeoutConfigOnFPGA(uintmax_t const val = 0) : rant_t(val) {}
 };
 
+/******************************\
+   Interrupt Barrier config
+\******************************/
+
+/**
+ * Configuration register of systime-correction barrier activation of playback executor.
+ */
+struct GENPYBIND(inline_base("*")) SystimeCorrectionBarrierConfigOnFPGA
+    : public common::detail::RantWrapper<SystimeCorrectionBarrierConfigOnFPGA, uint_fast16_t, 0, 0>
+{
+	constexpr explicit SystimeCorrectionBarrierConfigOnFPGA(uintmax_t const val = 0) : rant_t(val)
+	{}
+};
+
 /***********\
    SpikeIO
 \***********/
@@ -216,6 +230,7 @@ HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::FPGADeviceDNAOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::NullPayloadReadableOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::EventRecordingConfigOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::InstructionTimeoutConfigOnFPGA)
+HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::SystimeCorrectionBarrierConfigOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::ExternalPPUMemoryByteOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::ExternalPPUMemoryQuadOnFPGA)
 HALCO_GEOMETRY_HASH_CLASS(halco::hicann_dls::vx::ExternalPPUMemoryBlockSize)
diff --git a/include/halco/hicann-dls/vx/v2/coordinates.def b/include/halco/hicann-dls/vx/v2/coordinates.def
index 4448911e004018c04e4a01dae34a7f5f5578d1dd..bba10845bed54dd79256f4a1bca5136870dee03b 100644
--- a/include/halco/hicann-dls/vx/v2/coordinates.def
+++ b/include/halco/hicann-dls/vx/v2/coordinates.def
@@ -133,6 +133,7 @@ COORDINATE(ExternalPPUMemoryOnFPGA, halco::hicann_dls::vx::v2::ExternalPPUMemory
 COORDINATE(NullPayloadReadableOnFPGA, halco::hicann_dls::vx::v2::NullPayloadReadableOnFPGA)
 COORDINATE(EventRecordingConfigOnFPGA, halco::hicann_dls::vx::v2::EventRecordingConfigOnFPGA)
 COORDINATE(InstructionTimeoutConfigOnFPGA, halco::hicann_dls::vx::v2::InstructionTimeoutConfigOnFPGA)
+COORDINATE(SystimeCorrectionBarrierConfigOnFPGA, halco::hicann_dls::vx::v2::SystimeCorrectionBarrierConfigOnFPGA)
 COORDINATE(SpikeIOAddress, halco::hicann_dls::vx::v2::SpikeIOAddress)
 COORDINATE(SpikeIOConfigOnFPGA, halco::hicann_dls::vx::v2::SpikeIOConfigOnFPGA)
 COORDINATE(SpikeIOInputRouteOnFPGA, halco::hicann_dls::vx::v2::SpikeIOInputRouteOnFPGA)
diff --git a/include/halco/hicann-dls/vx/v2/fpga.h b/include/halco/hicann-dls/vx/v2/fpga.h
index 42a8e747b93aa594d282c2345bbb42f509a6dfdf..f9851907e984832492e3104d6b66f95a25d30a4c 100644
--- a/include/halco/hicann-dls/vx/v2/fpga.h
+++ b/include/halco/hicann-dls/vx/v2/fpga.h
@@ -28,6 +28,8 @@ using EventRecordingConfigOnFPGA GENPYBIND(visible) =
     halco::hicann_dls::vx::EventRecordingConfigOnFPGA;
 using InstructionTimeoutConfigOnFPGA GENPYBIND(visible) =
     halco::hicann_dls::vx::InstructionTimeoutConfigOnFPGA;
+using SystimeCorrectionBarrierConfigOnFPGA GENPYBIND(visible) =
+    halco::hicann_dls::vx::SystimeCorrectionBarrierConfigOnFPGA;
 using SpikeIOAddress GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOAddress;
 using SpikeIOConfigOnFPGA GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOConfigOnFPGA;
 using SpikeIOInputRouteOnFPGA GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOInputRouteOnFPGA;
diff --git a/include/halco/hicann-dls/vx/v3/coordinates.def b/include/halco/hicann-dls/vx/v3/coordinates.def
index 0027ee385f745000cfe09d09a524949b792f1767..1f7302aeef0d66bdab391fda9dea1aae4b774752 100644
--- a/include/halco/hicann-dls/vx/v3/coordinates.def
+++ b/include/halco/hicann-dls/vx/v3/coordinates.def
@@ -133,6 +133,7 @@ COORDINATE(ExternalPPUMemoryOnFPGA, halco::hicann_dls::vx::v3::ExternalPPUMemory
 COORDINATE(NullPayloadReadableOnFPGA, halco::hicann_dls::vx::v3::NullPayloadReadableOnFPGA)
 COORDINATE(EventRecordingConfigOnFPGA, halco::hicann_dls::vx::v3::EventRecordingConfigOnFPGA)
 COORDINATE(InstructionTimeoutConfigOnFPGA, halco::hicann_dls::vx::v3::InstructionTimeoutConfigOnFPGA)
+COORDINATE(SystimeCorrectionBarrierConfigOnFPGA, halco::hicann_dls::vx::v3::SystimeCorrectionBarrierConfigOnFPGA)
 COORDINATE(SpikeIOAddress, halco::hicann_dls::vx::v3::SpikeIOAddress)
 COORDINATE(SpikeIOConfigOnFPGA, halco::hicann_dls::vx::v3::SpikeIOConfigOnFPGA)
 COORDINATE(SpikeIOInputRouteOnFPGA, halco::hicann_dls::vx::v3::SpikeIOInputRouteOnFPGA)
diff --git a/include/halco/hicann-dls/vx/v3/fpga.h b/include/halco/hicann-dls/vx/v3/fpga.h
index 1b4eaf63500dc4e4998e04de189df94d7d4082db..0b2852f687919301e91c5a06f193bb74c5c683f4 100644
--- a/include/halco/hicann-dls/vx/v3/fpga.h
+++ b/include/halco/hicann-dls/vx/v3/fpga.h
@@ -28,6 +28,8 @@ using EventRecordingConfigOnFPGA GENPYBIND(visible) =
     halco::hicann_dls::vx::EventRecordingConfigOnFPGA;
 using InstructionTimeoutConfigOnFPGA GENPYBIND(visible) =
     halco::hicann_dls::vx::InstructionTimeoutConfigOnFPGA;
+using SystimeCorrectionBarrierConfigOnFPGA GENPYBIND(visible) =
+    halco::hicann_dls::vx::SystimeCorrectionBarrierConfigOnFPGA;
 using SpikeIOAddress GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOAddress;
 using SpikeIOConfigOnFPGA GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOConfigOnFPGA;
 using SpikeIOInputRouteOnFPGA GENPYBIND(visible) = halco::hicann_dls::vx::SpikeIOInputRouteOnFPGA;
diff --git a/pyhalco/test/pyhalco_test_hicann_dls_vx_v2.py b/pyhalco/test/pyhalco_test_hicann_dls_vx_v2.py
index 9d7a42074c55a49059c3af724f84d20755c734fe..60a78408f605dbd7c307bd264607ef4b2908f818 100644
--- a/pyhalco/test/pyhalco_test_hicann_dls_vx_v2.py
+++ b/pyhalco/test/pyhalco_test_hicann_dls_vx_v2.py
@@ -42,6 +42,7 @@ class Test_PyhalcoHICANNDLSvx(unittest.TestCase, PyhalcoTest):
     NullPayloadReadableOnFPGA => linear,iterable
     EventRecordingConfigOnFPGA => linear,iterable
     InstructionTimeoutConfigOnFPGA => linear,iterable
+    SystimeCorrectionBarrierConfigOnFPGA => linear,iterable
     SpikeIOAddress => linear,iterable
     SpikeIOConfigOnFPGA => linear,iterable
     SpikeIOInputRouteOnFPGA => linear,iterable
diff --git a/pyhalco/test/pyhalco_test_hicann_dls_vx_v3.py b/pyhalco/test/pyhalco_test_hicann_dls_vx_v3.py
index 9cf269b681e6baf08aaf8acae6a331d5d9a50a46..4db6320c5c05753afd064d75ff702c8cfdc60516 100644
--- a/pyhalco/test/pyhalco_test_hicann_dls_vx_v3.py
+++ b/pyhalco/test/pyhalco_test_hicann_dls_vx_v3.py
@@ -42,6 +42,7 @@ class Test_PyhalcoHICANNDLSvx(unittest.TestCase, PyhalcoTest):
     NullPayloadReadableOnFPGA => linear,iterable
     EventRecordingConfigOnFPGA => linear,iterable
     InstructionTimeoutConfigOnFPGA => linear,iterable
+    SystimeCorrectionBarrierConfigOnFPGA => linear,iterable
     SpikeIOAddress => linear,iterable
     SpikeIOConfigOnFPGA => linear,iterable
     SpikeIOInputRouteOnFPGA => linear,iterable